1. Field of the Invention
The present invention relates to a semiconductor device and a method of its fabrication, and more particularly to connection for multilevel metallization.
2. Description of the Related Art
Wiring is increasingly gaining in significance for the reliability and the performance of semiconductor integrated circuits (ICs) in a current movement to miniaturization. Problems in the wiring arise due to Joule effect in conductor regions. The interaction with electromigration (EM), the wiring can be completely destroyed. In order to avoid this, particular care must be exercised to avoid high and non-inform electrical resistances in a wiring process that should be suitable for dimensions in the 0.4 .mu.m range, for example, because of the high current densities that occur therein.
Reductions of conductor line (interconnect) widths and distances, and contact hole (via) diameters are demanded to realize higher packing densities in semiconductor ICs. A contact hole (via) having a greater depth to width ratio ("aspect ratio") is also demanded. Reduction of line widths results in increase in sheet resistance of the lines. Increase in sheet resistance needs to be suppressed without increasing thickness of film forming the lines. This is because increasing the film thickness results in Increased coupling capacity (parasite capacity) between the adjacent lines. Increased coupling capacity causes a drop in high-speed operation of semiconductor ICS. The thickness of the line forming film must be set as small as possible within an allowable range for current densities required for interconnects in higher level.
For manufacturing interconnection in the 0.4 micron range, constrictions at the upper level interconnect to contact plug interface must be prevented. However, misalignment will reduce overlapping area. Specifically, there occurs exposure of portion of upper end of contact plug by the upper level interconnect due to misalignment. If a tungsten film constitutes a major part of a contact plug and an aluminum alloy film constitutes a major part of an upper level interconnect, the interconnect exhibits more susceptibility to electromigration at area where current flows into the interconnect from the contact plug. When electromigration occurs, Voids form in the aluminum alloy film within the area right above the contact plug and in the neighborhood thereof. Resistivity of the interconnect increases because charged carriers cannot pass through the voids. This degrades the reliability of the upper level interconnects. Electromigration of aluminum atom provides flow of electric charge in the same direction as flow of electric current. It increases as electric densities through upper level interconnects increase. The boundary surface between the upper level interconnect and contact plug restricts the flow rate of electric charge of the electromigration. The area at the interface of the upper level interconnect to the upper end of the contact plug is less than the area of the upper and of the contact plug due to the misalignment. This means that the electric density at the interface is always higher than the electric density at the remote portion of the interconnect from the interface. The restriction and the local increase of electric density at the interface cause increased occurrence of electromigration at the interface.
This increase may be suppressed if a spacer of conductive film is formed over the sidewalls of the upper level interconnects. But, distances among the interconnects become small, increasing the coupling (parasite) capacity, decreasing high-speed operation of the semiconductor IC.
The reduction in area at the interface of the interconnection to the contact plug causes increased resistance at the interface. Thus,, power consumption is high at the upper level interconnects within the area where the electromigration tends to occur.
An object of the present invention is to suppress occurrence of electromigration at the interface of interconnect to contact plug without any substantial increase in coupling capacity between interconnects as well as suppression of increase in power consumption.